Oscillation ring delay test for high performance microprocessors

This paper proposes a new test scheme, oscillation ring test, and its assoc iated test circuit organization for delay fault testing for high performanc e microprocessors. For this test scheme, the outputs of the circuit under t est are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to dete ct whether the circuit is working normally or not. The sensitizable paths o f oscillation rings cover all circuit lines, detecting all gate delay fault s, a large part of hazard free robust path delay faults and all the stuck-a t faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used t o measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocess ors.