An FPGA implementation guide for some different types of serial-parallel multiplier structures

The multiplier is one of the most important components in the computing and reconfigurable computing systems, especially in the field of digital signa l processing (DSP). Hence, in this paper, a performance evaluation and comp arison (efficient area and moderate speed) for different serial-parallel mu ltiplier structures have been carried out for the case of their implementat ion by one of the programmable logic devices, such as a field programmable gate array (FPGA). The implementation of these structures for 8-bit paralle l operands has been executed by utilizing the XC4010E chip and Foundation s oftware package V1.3 from Xilinx. The implementation results illustrate the progress in the design area, saving and speeding up the design performance . (C) 2000 Elsevier Science Ltd. All rights reserved.