A novel fast technique for detecting voiding damage in IC interconnects

A novel technique has been developed, which is sensitive to the degree of v oiding damage induced in a wide-line interconnect test structure (Testing o f conductors, Preliminary Irish patent application, August 26th, 1998). The technique is based on the measurement of the scattering parameters (S-para meters) of a simple, metal-line test structure over a range of high frequen cies. The transmission-line parameter, G (leakage conductance), which is ca lculated from the S-parameter measurements, is shown to be sensitive to dis tribute voiding, especially in wider lines. This is significant for the fol lowing reasons: (1) the measurement is fast - a few seconds per test struct ure, (2) it can be performed at wafer level, (3) it does not rely on overst ressing of the metallization and (4) it is sensitive to the amount of voidi ng damage present in wide interconnect lines. Potential applications for th is technique are: (a) an in-line statistical reliability control (SRC) test for the detection of stress voids induced during processing, and (b) an in -line SRC test for electromigration when preceded by a suitable current pre -stress step. (C) 2000 Elsevier Science Ltd. All rights reserved.