We have newly developed a 1Gb Double Data Rate-Synchronous DRAM (DDR-SDRAM)
realizing 250Mbps/pin using a 0.18 mu m fabrication process. This 1Gb DDR-
SDRAM features (1) a Bi-Directional Delay (BDD) that realizes an internal c
lock generator achieving a low-jitter, small-area, and short lock time, (2)
a Quad-Coupled Receiver (QCR) to reduce the internal skew between rise inp
ut and fall input propagation delay time, and (3) an Inter-Bank Shared Redu
ndancy Scheme (ISR) with a Variable Unit Redundancy (VUR) to increase yield
.