Models that place design constraints on devices which are used to measure t
he leakage currents in high-resistivity semiconductor materials are present
ed. If these design constraints are met, these models can then be used to q
uantitatively predict the surface sheet resistance of devices which are dom
inated by surface leakage currents. As a result, a means is provided to dir
ectly compare passivation techniques which are developed to decrease surfac
e leakage currents. Furthermore, these models illustrate the necessity for
inclusion of relevant geometrical data on sample size and shape and electro
de configuration when reporting results of surface passivation techniques.
These models specifically examine the case where a de potential is applied
across two electrodes on the surface of a semiconductor substrate which has
a surface layer with lower resistivity than the bulk material. We describe
several of the more common configurations used in analyzing passivation te
chniques for compounds of Cd1-xZnxTe (CZT) used for room-temperature radiat
ion detection.