A front-end electronics module for the PHENIX Pad Chamber

A front-end electronics module (FEM) has been developed for the PHENIX Pad Chamber. The module's control functions are performed by the heap manager u nit, an FPGA-based circuit on the FEM. Each FEM processes signals from 2160 channels of front-end electronics (FEE). Data readout and formatting are p erformed by an additional FPGA-based circuit on the FEM. Three external sys tems provide initialization timing, and data information via serial interfa ces. This paper discusses the application of the heap manager, data formatt er, and serial interfaces to meet the specific control and data readout nee ds of the Pad Chamber subsystem. Unit functions, interfaces, timing, data f ormat, and communication rates will be discussed. In addition, subsystem is sues regarding mode control, serial architecture and functions, error handl ing and FPGA implementation and programming will be presented.