SEU testing of a novel hardened register implemented using standard CMOS technology

A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a stand ard submicron nonradiation hardened CMOS technology. This paper presents th e results of heavy ions tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-sectio n, without significant impact to die real estate, write time, or power cons umption.