The impact of software and CAE tools on SEU in field programmable gate arrays

Field programmable gate array (FPGA) devices, heavily used in spacecraft el ectronics, have grown substantially in size over the past few years, causin g designers to work at a higher conceptual level, with computer aided engin eering (CAE) tools synthesizing and optimizing the logic from a description . It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be use d to improve the SEU performance of a flip-flop, exploiting the configurabl e nature of FPGA technology and on-chip delay, parasitic resistive, and cap acitive circuit elements.