Use of COTS microelectronics in radiation environments

This paper addresses key issues for the cost-effective use of COTS (Commerc ially available Off The Shelf) microelectronics in radiation environments t hat enable circuit or system designers to manage risks and ensure mission s uccess. We review several factors and tradeoffs affecting the successful ap plication of COTS parts including (1) hardness assurance and qualification issues, (2) system hardening techniques, and (3) life-cycle costs. The pape r also describes several experimental studies that address trends in total- dose, transient, and single-event radiation hardness as COTS technology sca les to smaller feature sizes. As an example, the level at which dose-rate u pset occurs in Samsung SRAMs increases from 1.4x10(8) rad(Si)/s for a 256K SRAM to 7.7x10(9) rad(Si)/s for a 4M SRAM, indicating unintentional hardeni ng improvements in the design or process of a commercial technology. Additi onal experiments were performed to quantify variations in radiation hardnes s for COTS parts. In one study, only small (10-15%) variations were found i n the dose-rate upset and latchup thresholds for Samsung 4M SRAMs from thre e different date codes. In another study, irradiations of 4M SRAMs from Sam sung, Hitachi, and Toshiba indicate large differences in total-dose radiati on hardness. The paper attempts to carefully define terms and clear up misu nderstandings about the definitions of "COTS" and "radiation-hardened (RH)" technology.