Minimizing gain degradation in lateral PNP bipolar junction transistors using gate control

Gain degradation in lateral PNP bipolar junction transistors is minimized b y controlling the potential of a gate terminal deposited above the active b ase region. Gate biases that deplete the base during radiation exposure est ablish electric fields in the base oxide that limit the generation of oxide defects. Conversely, gate biases that accumulate the base during device op eration suppress gain degradation by decreasing the probability of carrier recombination with interface states. The results presented in this paper su ggest that, for gate controlled LPNP transistors designed for operation in radiation environments, a dynamic control of the gate potential improves th e transistor's radiation hardness and extend its operating life.