Scaling efforts to develop an advanced radiation-hardened CMOS process to s
upport a 4M SRAM are described. Issues encountered during scaling of transi
stor, isolation, and resistor elements are discussed, as well as the soluti
ons used to overcome these issues. Transistor data, total dose radiation re
sults, and the performance of navel resistors for prevention of single even
t upsets (SEU) are presented.