SRAM based re-programmable FPGA for space applications

An SRAM (static random access memory)-based reprogrammable FPGA (field prog rammable gate array) is investigated for space applications. A new commerci al prototype, named the RS family, was used as an example for the investiga tion. The device is fabricated in a 0.25 mu m CMOS technology. Its architec ture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of differe nt memories available on the device is evaluated. Heavy ion test data and S PICE simulations are used integrally to extract the threshold LET (linear e nergy transfer). Together with the saturation cross-section measurement fro m the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discu ssed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the m emories and employing EDAC (error detection and correction) at the device l evel are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are invest igated with interesting results. Preliminary heavy ion test data show no si gn of SEL (single event latch-up). With regard to ionizing radiation effect s, the increase in static leakage current (static I-CC) measured indicates a device tolerance of approximately 50krad(Si).