A 2-ns-access, 285-MHz, two-port cache macro using double global bit-line pairs

Authors
Osada, K Higuchi, H Ishibashi, K Hashimoto, N Shiozawa, K
Citation
K. Osada et al., A 2-ns-access, 285-MHz, two-port cache macro using double global bit-line pairs, IEICE TR EL, E83C(1), 2000, pp. 109-114
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON ELECTRONICS
ISSN journal
09168524 → ACNP
Volume
E83C
Issue
1
Year of publication
2000
Pages
109 - 114
Database
ISI
SICI code
0916-8524(200001)E83C:1<109:A22TCM>2.0.ZU;2-6
Abstract
We fabricated a 16-kB cache macro using 0.35-mu m quadruple-metal CMOS tech nology. This is a 285-MHz, two-port 16-kB (512 x 256 b) cache macro that ha s a 2-ns access time. This high-speed performance is enabled by a hierarchi cal bit-line architecture: that uses double global bit-line pairs (WGBs); a nd a high-speed timing-insensitive sense amplifier (ISA) that shortens the access time.