An emulated digital CNN implementation

A new emulated digital CNN Universal Machine chip architecture is introduce d and the main steps of the design process are shown in this paper. One cor e processor can be implemented on 2 x 2 mm(2) silicon area with a 0.35 mu m CMOS technology. Assuming an array of 24 processors on a chip, its speed i s lns/virtual cell/CNN iteration with 12 bit precision. This enables the ex ecution of over five hundred 3 x 3 convolution operations on each frame of a 240 x 320-pixel 25 fps digital image flow. Another new feature of the des ign is its variable precision capability. This allows the user to trade off precision for speed. The architecture supports some non-linear filter impl ementation as well.