Spike anneal: RTP processing at reduced thermal budget with applications to TiSi2 formation towards 0.1-mu m linewidths

Authors
Citation
E. Gerritsen, Spike anneal: RTP processing at reduced thermal budget with applications to TiSi2 formation towards 0.1-mu m linewidths, MICROEL ENG, 50(1-4), 2000, pp. 147-151
Citations number
7
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONIC ENGINEERING
ISSN journal
01679317 → ACNP
Volume
50
Issue
1-4
Year of publication
2000
Pages
147 - 151
Database
ISI
SICI code
0167-9317(200001)50:1-4<147:SARPAR>2.0.ZU;2-Z
Abstract
I report a way out of the narrowing of the temperature process window for f ormation of low resistivity C54-TiSi2 below 0.25-mu m linewidth. On one han d, higher temperatures would be required to overcome the increasing difficu lty of the C54-TiSi2 transformation. On the other hand, temperature should be lowered to avoid the increasing tendency to thermal agglomeration. A spi ke anneal, at higher temperature and shorter duration with high ramp-rate, is found to give full transformation on 0.25-mu m lines without parasitic e ffects and with a tighter resistance distribution. (C) 2000 Elsevier Scienc e B.V. All rights reserved.