Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology

A detailed study of copper contaminating steps performed during integration of multilevel Cu metallisation in dual damascene architecture has been per formed. Contamination at the wafer back and the bevel edge should make it d ifficult to use the same equipment for conventional technology and new copp er based technology. Several barrier materials have been claimed as efficie nt against copper diffusion. However, during process integration, contamina tion issues will be faced before deposition of the barrier layers. Heavy co ntamination can occur either during Cu chemical mechanical polishing (CMP) or during dielectric etching and via opening on top of contacted copper lin es. These residues, concentrated at the dielectric surface, could result in current leakage and shorts between interconnection lines. Several cleaning solutions to remove metal contamination are reviewed and their efficiencie s are compared. (C) 2000 Elsevier Science B.V. All rights reserved.