Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffu sion into silicon active zone that could seriously damage device performanc e, and into interlevel dielectric that could induce shorts or degrade diele ctric performance. This paper relates the integration of Cu-CVD with SiO2. Structures studied are SiO2 deposited on Cu-CVD, and SiO2/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO2 to act as diffusion barrie r and as an etch stop during the interconnect structure patterning. Both Si O2 and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH4 precursor with addition of, respectively, N 2O or NH3. Cu contamination is shown to occur during the dielectric deposit ion onto Cu, and is enhanced by the fluorine presence in the deposition cha mber. Deposition processes were evaluated in order to lower Cu contaminatio n in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper co ntamination during the dielectric deposition process. This issue can be add ressed by the optimization of the dielectric deposition process. (C) 2000 E lsevier Science B.V. All lights reserved.