Reduction in energy consumption by bootstrapped nMOS switches in reversible adiabatic CMOS circuits

For ultra-low-energy applications, bootstrapped reversible-energy-recovery logic (bRERL) is proposed, which is a reversible adiabatic CMOS logic and r equires an 8-phase clock. In bRERL, each transmission gate was replaced by a bootstrapped nMOS switch in the logic functional blocks of tRERL. Using S PICE simulations, it was confirmed that the bRERL circuit consumed less ene rgy and occupied less area than the tRERL circuit. The authors integrated a bRERL inverter chain with its 8-phase, clocked power generator in a test c hip, which was fabricated with 0.6 mu m CMOS technology. They also confirme d that they could minimise the energy consumption in the bRERL circuit by r educing the operating frequency until adiabatic and leakage losses were equ al.