Gate-level voltage scaling for low-power design using multiple supply voltages

The advent of portable and high-density devices has made power consumption a critical design concern. The authors address the problem of reducing powe r consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. First, a maximum-weighted independent s et formulation is used for voltage reduction on the noncritical part of the circuit. Secondly, a minimum-weighted separator set formulation is used to for gate sizing and to integrate the sizing procedure with a voltage scali ng procedure to enhance power saving for the whole circuit. The proposed me thods are evaluated using the MCNC benchmark circuits. An average of 19.12% power reduction has been achieved over the circuits having only one supply voltage.