Set of self-timed latches for high-speed VLSI

A set of novel self-tinted latches is introduced and analysed. These latche s have no back-to-back connection as in conventional self-timed latches, an d both inverting and noninverting outputs are evaluated simultaneously lead ing to higher operating frequencies. A novel type of cross-coupled inverter used in the proposed circuits implements static operation without the sign al fighting with the main driver during signal transition. The power consum ption of these latches is also comparable to, or less than, that of convent ional circuits. The proposed latches are designed using a 0.35 mu m CMOS te chnology. The comparison results indicate that the proposed active-low self -timed latch (ALSTL) improves speed by 22-34% over the conventional NAND SR latch, while for the active-high self-timed latch (AHSTL) the speed improv ements are 20-35% with less power as compared to the corresponding NOR SR l atch.