CMOS switched-op-amp-based sample-and-hold circuit

This paper presents a sample-and-hold design that is based on a switched-op -amp topology. Charge injection errors are greatly reduced by turning off t ransistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feedthrough error is mostly signal-independent and is cancelled out by a pseudodifferential top ology. Switched-op-amps are designed and fabricated in a 2-mu CMOS technolo gy. The measurement results show that the harmonics are at least 78 dB belo w the signal level. Both the measurement results from fabricated IC's and s imulation results suggest the potential benefits of this approach in compar ison to traditional switched-capacitor circuits.