PMD mitigation at 10Gbit/s using linear and nonlinear integrated electronic equaliser circuits

Citation
H. Bulow et al., PMD mitigation at 10Gbit/s using linear and nonlinear integrated electronic equaliser circuits, ELECTR LETT, 36(2), 2000, pp. 163-164
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
2
Year of publication
2000
Pages
163 - 164
Database
ISI
SICI code
0013-5194(20000120)36:2<163:PMA1UL>2.0.ZU;2-O
Abstract
A transversal filter (TF) and a decision feedback equaliser (DFE) have been manufactured as integrated electronic circuits in SiGe technology suitable for 10Gbit/s operation. Using these devices, electrical equalisers for imp lementation in optical receivers have been realised and the reduction in pe nalty induced by polarisation mode dispersion (PMD) has been experimentally analysed. A device consisting of the concatenation of a TF and DFE exhibit s the lowest residual penalty, < 3 dB for a PMD with a differential group d elay of < 80ps.