The TigerSHARC DSP architecture

Authors
Fridman, J Greenfield, Z
Citation
J. Fridman et Z. Greenfield, The TigerSHARC DSP architecture, IEEE MICRO, 20(1), 2000, pp. 66-76
Citations number
13
Categorie Soggetti
Computer Science & Engineering
Journal title
IEEE MICRO
ISSN journal
02721732 → ACNP
Volume
20
Issue
1
Year of publication
2000
Pages
66 - 76
Database
ISI
SICI code
0272-1732(200001/02)20:1<66:TTDA>2.0.ZU;2-E
Abstract
THIS HIGHLY PARALLEL DSP ARCHITECTURE BASED ON A SHORT-VECTOR MEMORY SYSTEM INCORPORATES TECHNIQUES FOUND IN GENERAL-PURPOSE COMPUTING. IT PROMISES SU STAINED PERFORMANCE CLOSE TO ITS PEAK COMPUTATIONAL RATES OF 900 MFLOPS (32 -BIT FLOATING-POINT) OR 3.6 BOPS (16-BIT FIXED-POINT).