An approach for detecting multiple faulty FPGA logic blocks

An approach is proposed to test FPGA logic blocks, including part of the co nfiguration memories used to control them. The proposed AND tree and OR tre e-based testing structure is simple and the conditions for constant testabi lity can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC 4000, and XC5200 families were studied. The proposed AND/OR approach was fo und to reduce the number of FPGA reprogrammings needed for testing;by up to a factor of seven versus direct methods of multiple faulty block detection .