Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable fdr the VLSI design of systolic array processor cells for perfo rming QR decomposition. This is based on an on-line CORDIC algorithm with a Constant scale factor and a latency independent of the wordlength. This ha s been derived through the extension of previously published CORDIC algorit hms. It is shown that simplifying the calculation of convergence bounds als o greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-mu CMOS standard cell process, indicate that 20 su ch QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.