Computation reordering: A novel transformation for low power DSP synthesis

A novel architectural transformation for low power synthesis of inner produ ct computational structures is presented. The proposed transformation reord ers the sequence of evaluation of the multiply-accumulate operations that f orm the inner products. Information related to both coefficients, which are statically determined, and data, which are dynamic, is used to drive the r eordering of computation, The reordering of computation reduces the switchi ng activity at the inputs of the computational units but inside them as wel l leading to power consumption reduction. Different classes of algorithms r equiring inner product computation are identified and the problem of comput ation reordering is formulated for each of them, The target architecture to which the proposed transformation applies is based on a power optimal memo ry organization and is described in derail. Experimental results for severa l DSP algorithms show that the proposed transformation leads to significant savings in net switching activity and thus in power consumption.