Memory chips with adjustable configurations

In this paper, we present the concept of Field Programmable Memory Cell Arr ays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays wh ich have proved their utility in design and rapid prototyping. Principles o f dynamic reconfigurability using programmable logic and programmable inter connect are incorporated into random access memories to achieve this flexib ility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configur ation of VaWiRAMs can be adjusted by setting a few configuration pins on th e memory chip. A VaWiRAM reconfigurable between widths 1 and W-max can be c onstructed with the extra cost of W-max - 1 pass gates, (W-max/2) 2-to-1 mu ltiplexers, and [log(2)[log(2)(lr) + 1]] mode pins. A novel scheme to overl ap the address pins with mode control pins and achieve the mode control wit h only one extra pin is also presented. The paper discusses the architectur e of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and int roduces the concept of FPMCAs.