Principles for language extensions to VHDL to support high-level modeling

This paper reviews proposals for extensions to VHDL to support high-level m odeling and places them within a taxonomy that describes the modeling requi rements they address. Many of the proposals focus on object-oriented extens ions, whereas this paper argues that extension of VHDL to support high-leve l modeling requires a broader review. The paper presents a detailed discuss ion of issues to be considered in adding high-level modeling extensions to VHDL, including concurrency and communication, abstraction using entity int erfaces, object-oriented data modeling, encapsulation, signal assignment se mantics, shared variables, multiple inheritance, genericity and synthesis. Emphasis is placed on the importance of designing simple orthogonal semanti c mechanisms that interact in well defined ways, and that integrate cleanly with existing language features.