CMOS high-frequency switched-capacitor filters for telecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use i n a switched digital video (SDV/VDSL) link is described. The highest availa ble clock frequency in the system is 51.84 MHz (f(s) = 2f(clock) = 103.68 M Hz for double sampling) while the three desired low-pass corner frequencies (f(c)) are 8, 12, and 20 MHz. The double-sampling, bilinear, elliptic, fif th-order switched-capacitor filter meets the desired -40-dB attenuation at 1,3f(c), and -30 dB at 1,25f(c), For the 12-MHz corner frequency setting, g iven the 2V(PP) differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB, The analog power dissipation is 125 mW from a 5-V power supply, The test results indicate t hat the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizin g metal-sandwich capacitors, performs as well as the special-layer analog c apacitors implementation, with a small reduction in the absolute corner fre quencies. The prototype IC's are fabricated in a 0.35-mu m 5-V (0.48 mu m d rawn) CMOS process.