A distributed selector IC using GaAs MESFET's with multilayer-interconnection structure

This paper describes novel high-speed selector circuits based on the distri buted circuit approach and their circuit design methodologies. Two types of distributed selectors are designed and fabricated using 0.16-mu m GaAs MES FET's with multilayer-interconnection structure. Both basically consist of eight stages of series-gated source-coupled field-effect transistor (FET) l ogic (SCFL) selector cell units laid out, in a distributed fashion. The sec ond circuit incorporates additional functions: a data input level shifter i n each cell to make an SCFL interface for the data input and a balun for si ngle-balance transformation of the clock input. A small-signal distributed amplifier design is extended to a large-signal distributed logic IC design, taking dynamic variations in transistor parameters into consideration, The error-free operation of both fabricated distributed selector IC's is confi rmed at up to 40 Gbit/s, and the first IC still exhibited eye opening with 130 -mV voltage swing of the inside measurement at 70 Gbit/s, which reaches 80% of f(T) of the fabricated FET. These distributed selector IC's success fully exhibit eye opening at higher bit rates compared to the conventional lumped-element design selector.