Sub-0.1 mu m gate etch processes: Towards some limitations of the plasma technology?

Citation
L. Desvoivres et al., Sub-0.1 mu m gate etch processes: Towards some limitations of the plasma technology?, J VAC SCI B, 18(1), 2000, pp. 156-165
Citations number
15
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Material Science & Engineering
Journal title
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B
ISSN journal
10711023 → ACNP
Volume
18
Issue
1
Year of publication
2000
Pages
156 - 165
Database
ISI
SICI code
1071-1023(200001/02)18:1<156:SMMGEP>2.0.ZU;2-R
Abstract
Gate structures with dimensions smaller than 0.1 mu m on gate oxides thinne r than 2 nm have been patterned in a high density plasma helicon source. Th e chemistry which seems best adapted uses an HBr/O-2 mixture ensuring high selectivity to the gate oxide and an etch anisotropy allowing the critical dimension control in the 0.1 mu m regime to be acceptable. Kinetic ellipsom etry I;as been used to measure silicon and SiO2 etch rates and carefully co ntrol the process in real time. X-ray photoelectron spectroscopy (XPS) stud ies have been performed to determine the chemical topography of SiO2 masked gate stacks with different aspect ratios. In particular, the chemical comp osition and thickness of the sidewall passivation layer have been determine d, We have also observed an unsuspected behavior of thin gate oxides during the overetch step pf the process. By combining XPS and spectroscopic;ellip sometry, we have attributed this behavior to reactive species penetration t hrough the thin gate oxide. This phenomenon could play an important role in the sub 0.1 mu m complementary metal-oxide-semiconductors process optimiza tion. (C) 2000 American Vacuum Society. [S0734-211X(00)06901-8].