Design and integration considerations for end-of-the roadmap ultrashallow junctions

Device simulations and response surface analysis have been-used to quantify the trade-offs and issues encountered in designing ultrashallow junctions- for the 250-50 nm generations of complimentary metal-oxide-semiconductor ul tralarge scale integration, technology. The design of contacting and extens ion junctions is performed to optimize short channel effects, performance, and reliability, while meeting the National Technology Roadmap for Semicond uctors off-state leakage specifications. A maxima in saturated drive curren t is observed for an intermediate extension junction depth (similar to 20 n m for 100 nm technology): shallower junctions lead to higher series resista nce, and deeper junctions result in more severe short channel effects. The gate-to-junction overlap required to preserve drive current was seen to dep end on junction abruptness. For a perfectly abrupt junction, it is not nece ssary for the gate to overlap the junction. Performance depends on many par ameters, including: overlap of gate to extension junction, junction capacit ance, and parasitic series resistance, which depends on the doping gradient at the junction (spreading resistance), the extension series resistance, a nd the contact resistance. Extraction of these parameters using I-V or C-V measurements can potentially lead to erroneous conclusions about lateral ju nction excursion and abruptness. (C) 2000 American Vacuum Society. [S0734-2 11X(00)05801-7].