Front end of line considerations far progression beyond the 100 nm node ultrashallow junction requirements

For complementary metal-oxide-semiconductor (CMOS) technology to meet the d emanding I scaling requirements for ultrashallow junctions and the low cont act resistivity necessary for device fabrication below the 100 nm technolog y node, significant technological barriers will need to be overcome. Numero us solutions have been proposed and a considerable amount of research and d evelopment is currently in progress to determine which, if any, of the prop osed processes can provide a definitive cost-effective solution that simult aneously meets all CMOS source and drain requirements. In this article, we present a brief overview of some of the techniques that have been proposed for ultrashallow junction and low contact resistance formation and that are . currently at the forefront for front end of line (FEOL) consideration. Th e current status of each potential technological solution is reviewed and w e will highlight the advantages and disadvantages associated with each. The FEOL process areas that we will restrict our discussion to include convent ional and alternative doping and annealing techniques. Our goal is to indic ate the current status of the research and development of these novel techn iques for the formation of ultrashallow junctions and low resistivity conta cts and to indicate the barriers that must be overcome in each process to m ake it a viable, cost effective technique. (C) 2000 American Vacuum Society . [S0734-211X(00)00301-8].