Practicalities and limitations of scanning capacitance microscopy for routine integrated circuit characterization

We have imaged several n-type metal-oxide-semiconductor transistors with di fferent source and drain architectures to assess the feasibility of extract ing useful figures of merit, such as the effective channel length of a devi ce, from the data. By varying the de bias on the sample we observe a shift of the junction position in the image and consider how best to interpret a set of voltage dependent images produced for a single sample. Careful atten tion is paid to the effects of surface variation from sample preparation an d tip wear during an experiment by considering the scanning capacitance mic roscopy signal in the substrate as a function of applied de bias. (C) 2000 American Vacuum Society. [S0734-211X(00)05901-1].