Functional validation of mixed hardware/software systems based on specification, partitioning, and simulation of test cases

Tecs is a test case development methodology for the functional validation o f large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-dow n test case development process including test case specification, validati on, partitioning and implementation. The test case development process addr esses the functional validation of the system and its components such as AS ICs, boards, HW and software modules; it does not facilitate timing or perf ormance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Te st cases are specified, using a special purpose formalism, and validated be fore they are applied to the system under test. Furthermore, we propose a t echnique to partition test cases corresponding to the partitioning of the s ystem into sub-systems and components. This technique can significantly red uce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system m odel need only be simulated with a reduced set of stimuli to validate the i nterfaces between sub-systems. We present a test case specification languag e and tools that support the proposed methodology. The validation of a swit ching function illustrates methodology, language, and tools.