COMPILATION METHODS FOR THE ADDRESS CALCULATION UNITS OF EMBEDDED PROCESSOR SYSTEMS

An essential component of today's embedded system is an instruction-se t processor running real-time software. All variations of these core c omponents contain at least the minimum data-flow processing capabiliti es, while a certain class contain specialized units for highly data-in tensive operations for Digital Signal Processing (DSP). For the requir ed level of memory interaction, the parallel executing Address Calcula tion Unit (ACU) is often used to tune the architecture to the memory a ccess characteristics of the application. The design of the ACU is per formance critical. In today's typical design how this design task is s omewhat driven by intuition as the transformation from application alg orithm to architecture is complex and the exploration space is immense . Automatic utilities to aid the designer are essential; however, the key compilation techniques which map high-level language constructs on to addressing units have lagged far behind the emergence of these unit s. This paper presents a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. In addition to being an enhancement to existing compiler syst ems, the ArrSyn utility may be used as an aid to architecture explorat ion. A simple specification of the addressing resources and basic oper ations drives the available transformations and allows the designer to quickly evaluate the effects on speed and code size of his/her algori thm. Thus, the designer can tune the design of the ACU toward the appl ication constraints. ArrSyn has been successfully used together with a C compiler developed for a VLIW architecture for an MPEG audio decodi ng application. The combination of these methods with the C compiler s howed on average a 39% speedup and 29% code size reduction for a repre sentative set of DSP benchmarks.