Cascaded parallel oversampling sigma-delta modulators

Based on the well-known time-interleaved modulator (TIM), a new cascade-par allel architecture of oversampling sigma-delta analog-to-digital converters is proposed. While retaining the speed advantage of TIM, the new architect ure gives a general method to effectively suppress the influence of circuit nonidealities, especially coefficient mismatches, on the converter's resol ution. Such influence is a serious problem in the practical realization of TIM. Simulation results of examples of both TIM and the new architecture ar e given for comparison, In addition to its improved performance, the new ar chitecture turns out to be quite simple, Therefore it can be a practical ap proach to extend the use of sigma-delta analog-to-digital conversion to hig h-speed applications.