A BIST scheme for RTL circuits based on symbolic testability analysis

This paper introduces a novel scheme for testing register-transfer level (R TL) controller/data paths using built-in self-test (BIST), The scheme uses the controller netlist and the data path of a circuit to extract a test con trol/data flow (TCDF) graph. This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test som e of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDF's, a few test multip lexers are added at suitable points in the circuit to increase its controll ability and observability, The test environment of an operation (variable) guarantees the existence of a path from the primary inputs of the circuit t o the inputs of the module (register) to which the operation (variable) is mapped, and a path from the output of the module (register) to a primary ou tput of the circuit. Since the search for a test environment is done symbol ically, it is very fast and needs to be done only once for each module or r egister in the circuit, This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators wh ich are placed only at the primary inputs of the circuit. The test response s can be analyzed with signature analyzers which are only placed at the pri mary outputs of the circuit, Unlike many RTL BIST schemes, an increase in t he data path bit-width does not adversely impact the complexity of our test ability analysis scheme since the analysis is symbolic. Every module in the module library is made random-pattern testable, whenever possible, using g ate-level testability insertion techniques, This is a one-time cost. Finall y, a BIST controller is synthesized to provide the necessary control signal s to form the different test environments during testing, and a BIST archit ecture is superimposed on the circuit, Experimental results on a number of industrial and university benchmarks show that high fault coverage (> 99 %) can be obtained with our scheme. The average area overhead of the scheme i s 6.9 % which is much lower than many existing logic-level BIST schemes. Th e average delay overhead is only 2.5 %, The test application time to achiev e the high fault coverage for the whole circuit is also quite low.