Speed and area tradeoffs in cluster-based FPGA architectures

One way to reduce the delay and area of field-programmable gate arrays (FPG A's) is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnectio ns. In this paper, we empirically evaluate FPGA architectures with logic cl usters ranging in size from 1 to 20, and show that compared to architecture s with size 1 clusters, architectures with size 8 clusters have 23% less de lay (30% faster clock speed) and require 14% less area. We also show that F PGA architectures with large cluster sizes can significantly reduce design compile time-an increasingly important concern as the logic capacity of FPG A's rises. For example, an architecture that uses size 20 clusters requires seven times less compile time than an architecture with size 1 clusters.