High-performance energy-efficient D-flip-flop circuits

Authors
Ko, UM Balsara, PT
Citation
Um. Ko et Pt. Balsara, High-performance energy-efficient D-flip-flop circuits, IEEE VLSI, 8(1), 2000, pp. 94-98
Citations number
9
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN journal
10638210 → ACNP
Volume
8
Issue
1
Year of publication
2000
Pages
94 - 98
Database
ISI
SICI code
1063-8210(200002)8:1<94:HEDC>2.0.ZU;2-R
Abstract
This paper investigates performance, power and energy efficiency of several CMOS master-slave D-flip-flops (DFF's). To improve performance and energy efficiency, a push-pull DFF and a push-pull isolation DFF are proposed, Amo ng the five DFF's compared, the proposed push-pull isolation circuit is fou nd to be the fastest with the best energy efficiency, Effects of using a do uble-pass-transistor logic (DPL) circuit and tri-state push-pull driver are also studied, Last, metastability characteristics of the five DFF's are al so analyzed.