Design of VHDL-based totally self-checking finite-state machine and data-path descriptions

This paper presents a complete methodology to design a totally self-checkin g (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifica tions. The control part of the system is designed to be self-checking by ad opting a state assignment providing a constant Hamming distance between eac h pair of binary codes. The design of the data path is based on both classi cal methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a nu mber of VHDL circuits.