SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide

An investigation of an SiGe CMOS process fulfilling low-thermal-budget requ irements was carried out. Three different undoped layers were grown success ively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap laye r. The Ge concentration of the SiGe layer was either uniform 20% or linearl y graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used a s gate dielectrics. The annealing was performed at relatively modest temper atures. The SiGe p-MOSFETs were compared to the Si reference devices. We re port an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.