Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger

The lateral SCR devices used in CMOS on-chip ESD protection circuits are re viewed. Such SCR devices had been found to be accidentally triggered by noi se pulses when the ICs are operated in the application systems. A cascoded design is therefore proposed to safely apply the LVTSCR devices for whole-c hip ESD protection in CMOS ICs without causing unexpected operation errors or latchup danger. The temperature dependence on the holding voltage of the cascoded LVTSCRs has been investigated in detail. From the experimental ve rification, the cascoded LVTSCRs can be fully turned on within a time below 20 ns. The ESD robustness per layout area of the three-cascoded LVTSCRs ca n be 0.83 V/mu m(2) in a 0.35-mu m silicide CMOS process without using the extra silicide-blocking and ESD-implant masks, whereas the ESD robustness o f the gate-grounded NMOS is only 0.25 V/mu m(2). Such cascoded LVTSCRs with a tunable holding voltage greater than VDD can provide CMOS ICs with effec tive component-level ESD protection but without causing catchup danger if i t is accidentally triggered by the system-level overshooting or undershooti ng noise pulses. (C) 2000 Elsevier Science Ltd. All rights reserved.