DSP implementation of self-synchronised chaotic encoder decoder

Authors
Penaud, S Guittard, J Bouysse, P Quere, R
Citation
S. Penaud et al., DSP implementation of self-synchronised chaotic encoder decoder, ELECTR LETT, 36(4), 2000, pp. 365-366
Citations number
6
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
4
Year of publication
2000
Pages
365 - 366
Database
ISI
SICI code
0013-5194(20000217)36:4<365:DIOSCE>2.0.ZU;2-0
Abstract
A general structure for a chaotic encoder/decoder pair with nonlinear funct ion is described. Different equations can be used with this structure. The encoder is a nonlinear recursive filter with finite precision. Simulation r esults and a digital signal processor implementation of this system are pre sented.