A contention-free Tbit/sec packet-switching architecture for ATM over WDM:networks

Future high-speed switches and routers will be expected to support a large number of ports at high line rates carrying traffic with diverse statistica l properties. Accordingly, scheduling mechanisms will be required to handle Tbit/sec aggregated capacity while providing quality of service (QoS) guar antees. In this paper a novel high-capacity switching scheme for ATM/WDM ne tworks is presented. The proposed architecture is contention-free, scalable , easy to implement and requires no internal "speedup." Non-uniform destina tion distribution and bursty cell arrivals are examined when studying the s witching performance. Simulation results show that at an aggregated through put of 1 Tbit/sec, low latency is achieved, yielding a powerful solution fo r high-performance packet-switch networks.