A 1.2 V, 30 MIPS, 0.3 mA/MIPS and 200 MIPS, 0.58 mA/MIPS digital signal processors

High-speed and low-power DSPs have been developed for versatile application s, especially for digital communications. These DSPs contain a 16-bit fixed point DSP core with multiple buses, highly tuned instruction set and low-p ower architecture, featuring 0.45 mA/MIPS, 100-120 MIPS performance by a si ngle CPU core, 200 MIPS performance by dual CPU core architecture, respecti vely and also contain a 1.2 V low-voltage DSP core with 30 MIPS performance for super low-power applications. In this paper, new architecture VIA2 pro gramming ROM for high-speed and new D flip-flop circuit considering the imp act of pocket implantation process for low power are discussed, including k ey C-MOS process technology.