A low-voltage 42.4 G-BPS single-ended read-modify-write bus and programmable page-sire on a 3D frame-buffer

Various kinds of high bandwidth architecture using the embedded DRAM techno logy have been presented previously. In most cases, they use wide bus imple mentation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-m odify-write bus increases the bandwidth twice as high, while it maintains t he same bus size and the same bus speed. The data-bus comprises 1 k-bit rea d-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a f requency of 166 MHz: A programmable page-size reduces the page miss-rate an d efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D fr ame-buffer to achieve 42.4 G-BPS bandwidth.