A CAD-compatible SOI-CMOS gate array using 0.35 mu m partially-depleted transistors

This paper describes a 0.35 mu m SOI-CMOS gate array using partially-deplet ed transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) k ink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and pow er-line wiring, the SOI-CMOS gate array also allows the use of the cell lib raries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabri cated using a 0.35 mu m SOI-CMOS gate array with 560k raw gates. The LSI op erated at 156 Mbps at 2.0 V, while consuming 71% less power than using a ty pical 0.35 mu m 3.3 V bulk-CMOS gate array.