A 10-bit 3-Msample/s CMOS multipath multibit cyclic ADC

A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs wi th a small chip-area of 1.5 mm(2) and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-mu m CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-d rive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit-+(one redundant bit)) was optimal fo r achieving 10-bit resolution with a small chip-area and low power consumpt ion given a required conversion time of 0.33 mu s. Our multipath architectu re cut power consumption by 30% compared to conventional cyclic A/D convert ers. By adding one signal path between the residue amplifier and the four b it subADC, the settling timing requirement can be relaxed, and the amplifie r's power consumption thus reduced.