A highly linear open-loop full CMOS high-speed sample-and-hold stage

Based on a cascode-driver source-follower buffer and a passive sampling arc hitecture, we have implemented a differential sample-and-hold circuit in a 0.8 mu m digital CMOS process. The buffer which eliminates channel length m odulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-lo op CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 1 0 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 V p-p 20 MHz at a 101 MHz sampling rate.